The present invention relates generally to data processing systems and more particularly to a technique by which two numbers are multiplied in such system.
Numerous techniques for multiplying two numbers are known in the prior art. Some such techniques are discussed in the book entitled "Digital Computer Design Fundamentals" by Y. Chu, published by McGraw-Hill Book Company, Inc., 1962. Two United States patents illustrating multiplication apparatus are U.S. Pat. No. 3,551,663 issued on Dec. 29, 1970 and U.S. Pat. No. 3,641,331 issued on Feb. 8, 1972. Each of these multiplication techniques of the prior art have certain advantages and disadvantages. For example, some such techniques require a rather large amount of logic in order to decrease the time of the multiplication process, and on the other hand some such techniques although requiring minimal logic take an extensive period of time to provide the result of the multiplication. Accordingly, it is important in most cases that a balance be achieved between the cost and space required for additional logic circuitry and the time required to perform such multiplication. An additional consideration in the multiplication process is the sign of the multiplier and the multiplicand. Some such multiplication techniques require special treatment for a negative signed number. For example, in some such techniques, the negative number must first be converted to a positive number via for example taking the so-called twos complement of such number. For two negative numbers, to be multiplied, then both such numbers must be converted to positive numbers. Obviously, the requirement to initialize the numbers to be multiplied based on their sign requires additional time and accordingly in some cases is not tolerable.
It is accordingly a primary object of the present invention to provide a multiplication technique in a data processing system which improves and which minimizes the time for the multiplication process particularly with respect to negative numbers.